[PR #2797] [MERGED] Implementing DS_SUB_U32, DS_INC_U32, DS_DEC_U32. #2988

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opened 2026-02-27 22:02:01 +03:00 by kerem · 0 comments

kerem commented

2026-02-27 22:02:01 +03:00

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📋 Pull Request Information

Original PR: https://github.com/shadps4-emu/shadPS4/pull/2797
Author: @diegolix29
Created: 4/16/2025
Status: ✅ Merged
Merged: 4/17/2025
Merged by: @squidbus

Base: main ← Head: More-opcodes

📝 Commits (3)

9c1827c Implementing DS_SUB_U32, DS_INC_U32, DS_DEC_U32, DS_WRITE_SRC2_B32, DS_WRITE_SRC2_B64.
bbf89cd Added ir instructions for new opcodes.
981b3e4 Suggestions

📊 Changes

7 files changed (+89 additions, -0 deletions)

View changed files

📝 src/shader_recompiler/backend/spirv/emit_spirv_atomic.cpp (+21 -0)
📝 src/shader_recompiler/backend/spirv/emit_spirv_instructions.h (+4 -0)
📝 src/shader_recompiler/frontend/translate/data_share.cpp (+42 -0)
📝 src/shader_recompiler/frontend/translate/translate.h (+3 -0)
📝 src/shader_recompiler/ir/ir_emitter.cpp (+12 -0)
📝 src/shader_recompiler/ir/ir_emitter.h (+4 -0)
📝 src/shader_recompiler/ir/opcodes.inc (+3 -0)

📄 Description

Based on AMD GCN ISA documentaion this pr add some of the missing opcode cases for read and write memory(DS), this is my first implementation of this cases so feel free to correct me if i missed something. Most of the implementations are based on the already done ones. This will only benefit games that use shared memory but for the long run i guess is better to add them first instead of being needed.

_{🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.}

## 📋 Pull Request Information **Original PR:** https://github.com/shadps4-emu/shadPS4/pull/2797 **Author:** [@diegolix29](https://github.com/diegolix29) **Created:** 4/16/2025 **Status:** ✅ Merged **Merged:** 4/17/2025 **Merged by:** [@squidbus](https://github.com/squidbus) **Base:** `main` ← **Head:** `More-opcodes` --- ### 📝 Commits (3) - [`9c1827c`](https://github.com/shadps4-emu/shadPS4/commit/9c1827cb455b40b9e087ba0b5f1b11dc68eb56f9) Implementing DS_SUB_U32, DS_INC_U32, DS_DEC_U32, DS_WRITE_SRC2_B32, DS_WRITE_SRC2_B64. - [`bbf89cd`](https://github.com/shadps4-emu/shadPS4/commit/bbf89cd3db3a6c75697739e0d6d434f1cdfd6224) Added ir instructions for new opcodes. - [`981b3e4`](https://github.com/shadps4-emu/shadPS4/commit/981b3e4ddccfd7832fbe689ad47db663ba457019) Suggestions ### 📊 Changes **7 files changed** (+89 additions, -0 deletions) <details> <summary>View changed files</summary> 📝 `src/shader_recompiler/backend/spirv/emit_spirv_atomic.cpp` (+21 -0) 📝 `src/shader_recompiler/backend/spirv/emit_spirv_instructions.h` (+4 -0) 📝 `src/shader_recompiler/frontend/translate/data_share.cpp` (+42 -0) 📝 `src/shader_recompiler/frontend/translate/translate.h` (+3 -0) 📝 `src/shader_recompiler/ir/ir_emitter.cpp` (+12 -0) 📝 `src/shader_recompiler/ir/ir_emitter.h` (+4 -0) 📝 `src/shader_recompiler/ir/opcodes.inc` (+3 -0) </details> ### 📄 Description Based on AMD GCN ISA documentaion this pr add some of the missing opcode cases for read and write memory(DS), this is my first implementation of this cases so feel free to correct me if i missed something. Most of the implementations are based on the already done ones. This will only benefit games that use shared memory but for the long run i guess is better to add them first instead of being needed. --- <sub>🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.</sub>