[PR #2082] [MERGED] shader_recompiler: Fix V_CMP_U_F32 #2478

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opened 2026-02-27 22:00:04 +03:00 by kerem · 0 comments

kerem commented

2026-02-27 22:00:04 +03:00

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📋 Pull Request Information

Original PR: https://github.com/shadps4-emu/shadPS4/pull/2082
Author: @squidbus
Created: 1/7/2025
Status: ✅ Merged
Merged: 1/7/2025
Merged by: @georgemoralis

Base: main ← Head: fix-cmp

📝 Commits (1)

1b77fde shader_recompiler: Fix V_CMP_U_F32

📊 Changes

1 file changed (+1 additions, -1 deletions)

View changed files

📝 src/shader_recompiler/frontend/translate/vector_alu.cpp (+1 -1)

📄 Description

Spotted this in CUSA28193, which has shader code like V_CMP_U_F32(value, value) ? 0 : value. There is a typo in the AMD ISA docs for GCN; V_CMP_U_F32 is supposed to beD.u = (isNaN(S0) || isNaN(S1)), not D.u = (!isNaN(S0) || !isNaN(S1)). This is supported by checking LLVM and Mesa compilers instruction usage, as well as docs for future ISA revisions listing it as D[threadId] = (isNan(S0) || isNan(S1)).

_{🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.}

## 📋 Pull Request Information **Original PR:** https://github.com/shadps4-emu/shadPS4/pull/2082 **Author:** [@squidbus](https://github.com/squidbus) **Created:** 1/7/2025 **Status:** ✅ Merged **Merged:** 1/7/2025 **Merged by:** [@georgemoralis](https://github.com/georgemoralis) **Base:** `main` ← **Head:** `fix-cmp` --- ### 📝 Commits (1) - [`1b77fde`](https://github.com/shadps4-emu/shadPS4/commit/1b77fde802e86ee776ab8e2f2284fa645cda3227) shader_recompiler: Fix V_CMP_U_F32 ### 📊 Changes **1 file changed** (+1 additions, -1 deletions) <details> <summary>View changed files</summary> 📝 `src/shader_recompiler/frontend/translate/vector_alu.cpp` (+1 -1) </details> ### 📄 Description Spotted this in CUSA28193, which has shader code like `V_CMP_U_F32(value, value) ? 0 : value`. There is a typo in the AMD ISA docs for GCN; `V_CMP_U_F32` is supposed to be`D.u = (isNaN(S0) || isNaN(S1))`, not `D.u = (!isNaN(S0) || !isNaN(S1))`. This is supported by checking LLVM and Mesa compilers instruction usage, as well as docs for future ISA revisions listing it as `D[threadId] = (isNan(S0) || isNan(S1))`. --- <sub>🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.</sub>