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[PR #1801] [MERGED] ir: Add heuristic based LDS barrier pass #2314
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📋 Pull Request Information
Original PR: https://github.com/shadps4-emu/shadPS4/pull/1801
Author: @raphaelthegreat
Created: 12/16/2024
Status: ✅ Merged
Merged: 12/19/2024
Merged by: @georgemoralis
Base:
main← Head:lds-barr📝 Commits (2)
c5f065bir: Add heuristic based LDS barrier pass875428elds_barriers: Limit to nvidia📊 Changes
6 files changed (+55 additions, -0 deletions)
View changed files
📝
CMakeLists.txt(+1 -0)📝
src/shader_recompiler/ir/passes/ir_passes.h(+5 -0)➕
src/shader_recompiler/ir/passes/shared_memory_barrier_pass.cpp(+46 -0)📝
src/shader_recompiler/profile.h(+1 -0)📝
src/shader_recompiler/recompiler.cpp(+1 -0)📝
src/video_core/renderer_vulkan/vk_pipeline_cache.cpp(+1 -0)📄 Description
Sometimes shaders can use shared memory without appropriate barriers in ISA level. This is probably because compiler optimized them away as it found them not needed (local workgroup size 64 for example makes barriers not necessary). This adds a new IR pass that attempts to insert such barriers to avoid device loss issues and graphics artifacts on NVIDIA.
Inserting barriers right after data share write instructions is not possible as we must have the barrier be outside of the non-uniform conditional block. The process is a bit naive at the moment, but it involves walking the generated AST and for shaders that use shared memory it inserts barriers after all zero-depth divergent conditional blocks.
The zero-depth clause prevents insertion of barriers already inside non-uniform blocks as that can cause issues since not all threads are executing that block. A block is deemed non-uniform if its condition contains gl_LocalInvocationId, which is simple and effective for now, but by far not exhaustive
🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.