[PR #745] [MERGED] Implement V_MOVREL variants #1748

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opened 2026-02-27 21:13:48 +03:00 by kerem · 0 comments

kerem commented

2026-02-27 21:13:48 +03:00

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📋 Pull Request Information

Original PR: https://github.com/shadps4-emu/shadPS4/pull/745
Author: @baggins183
Created: 9/3/2024
Status: ✅ Merged
Merged: 9/6/2024
Merged by: @raphaelthegreat

Base: main ← Head: v_movrels

📝 Commits (2)

a24945b shader_recompiler: Implement V_MOVRELS_B32, V_MOVRELD_B32,
0f6d75b fix runtime info after rebase

📊 Changes

11 files changed (+110 additions, -6 deletions)

View changed files

📝 src/shader_recompiler/backend/spirv/emit_spirv.cpp (+8 -0)
📝 src/shader_recompiler/backend/spirv/emit_spirv_instructions.h (+2 -0)
📝 src/shader_recompiler/frontend/translate/translate.cpp (+4 -4)
📝 src/shader_recompiler/frontend/translate/translate.h (+6 -1)
📝 src/shader_recompiler/frontend/translate/vector_alu.cpp (+55 -0)
📝 src/shader_recompiler/ir/ir_emitter.cpp (+8 -0)
📝 src/shader_recompiler/ir/ir_emitter.h (+2 -0)
📝 src/shader_recompiler/ir/opcodes.inc (+2 -0)
📝 src/shader_recompiler/ir/passes/ssa_rewrite_pass.cpp (+19 -1)
📝 src/shader_recompiler/runtime_info.h (+1 -0)
📝 src/video_core/renderer_vulkan/vk_pipeline_cache.cpp (+3 -0)

📄 Description

shader_recompiler: Implement V_MOVRELS_B32

Generates a ton of OpSelects to hardcode reading from the VGPR at src
index if the index is equal to 1..max_allocated_vgpr. Then do that
again to choose and write the dst vgpr

Also add support for reading/writing m0 register.

_{🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.}

## 📋 Pull Request Information **Original PR:** https://github.com/shadps4-emu/shadPS4/pull/745 **Author:** [@baggins183](https://github.com/baggins183) **Created:** 9/3/2024 **Status:** ✅ Merged **Merged:** 9/6/2024 **Merged by:** [@raphaelthegreat](https://github.com/raphaelthegreat) **Base:** `main` ← **Head:** `v_movrels` --- ### 📝 Commits (2) - [`a24945b`](https://github.com/shadps4-emu/shadPS4/commit/a24945b9528e40fc9e849bc082eda75b8f85a848) shader_recompiler: Implement V_MOVRELS_B32, V_MOVRELD_B32, - [`0f6d75b`](https://github.com/shadps4-emu/shadPS4/commit/0f6d75b4213cb35b694c6e794e504183e355bd87) fix runtime info after rebase ### 📊 Changes **11 files changed** (+110 additions, -6 deletions) <details> <summary>View changed files</summary> 📝 `src/shader_recompiler/backend/spirv/emit_spirv.cpp` (+8 -0) 📝 `src/shader_recompiler/backend/spirv/emit_spirv_instructions.h` (+2 -0) 📝 `src/shader_recompiler/frontend/translate/translate.cpp` (+4 -4) 📝 `src/shader_recompiler/frontend/translate/translate.h` (+6 -1) 📝 `src/shader_recompiler/frontend/translate/vector_alu.cpp` (+55 -0) 📝 `src/shader_recompiler/ir/ir_emitter.cpp` (+8 -0) 📝 `src/shader_recompiler/ir/ir_emitter.h` (+2 -0) 📝 `src/shader_recompiler/ir/opcodes.inc` (+2 -0) 📝 `src/shader_recompiler/ir/passes/ssa_rewrite_pass.cpp` (+19 -1) 📝 `src/shader_recompiler/runtime_info.h` (+1 -0) 📝 `src/video_core/renderer_vulkan/vk_pipeline_cache.cpp` (+3 -0) </details> ### 📄 Description shader_recompiler: Implement V_MOVRELS_B32 Generates a ton of OpSelects to hardcode reading from the VGPR at src index if the index is equal to 1..max_allocated_vgpr. Then do that again to choose and write the dst vgpr Also add support for reading/writing m0 register. --- <sub>🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.</sub>