[PR #613] [MERGED] shader_recompiler: constant propagation bitwise operations + S_CMPK_EQ_U32 fix #1666

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opened 2026-02-27 21:13:29 +03:00 by kerem · 0 comments

kerem commented

2026-02-27 21:13:29 +03:00

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📋 Pull Request Information

Original PR: https://github.com/shadps4-emu/shadPS4/pull/613
Author: @0xsegf4ult
Created: 8/27/2024
Status: ✅ Merged
Merged: 8/28/2024
Merged by: @raphaelthegreat

Base: main ← Head: gcn_opcodes

📝 Commits (7)

ad52474 rebase on main branch impl of V_LSHL_B64
de7f6e1 remove V_LSHR_B64
64bacb2 fix S_CMPK_EQ_u32
b0d300b fix conflicts
0fda82c fix broken merge
19c3569 remove duplicate cases
01931cc remove duplicate declaration

📊 Changes

7 files changed (+29 additions, -4 deletions)

View changed files

📝 src/shader_recompiler/backend/spirv/emit_spirv_instructions.h (+1 -0)
📝 src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp (+7 -0)
📝 src/shader_recompiler/frontend/translate/scalar_alu.cpp (+1 -1)
📝 src/shader_recompiler/ir/ir_emitter.cpp (+12 -2)
📝 src/shader_recompiler/ir/ir_emitter.h (+1 -1)
📝 src/shader_recompiler/ir/opcodes.inc (+1 -0)
📝 src/shader_recompiler/ir/passes/constant_propagation_pass.cpp (+6 -0)

📄 Description

Implemented BitwiseAnd64 IR opcode and added it with BitwiseOr64 to the constant propagation pass
Fixed S_CMPK_EQ_U32 to use the correct operand

Currently S_CMPK_EQ_U32 uses src[0] which is not defined for a SOPK instruction and this code always fails an assertion as the operand field is left undefined.

const IR::U32 src0{GetSrc(inst.src[0])};

I moved this to inst.dst[0] as specified in the ISA documentation and in line with how the decoder parses SOPK instructions

S_CMPK_EQ_U32: SCC = (D.u == SIMM16).

void GcnDecodeContext::decodeInstructionSOPK(u32 hexInstruction) {
    u32 sdst = bit::extract(hexInstruction, 22, 16);
    u32 op = bit::extract(hexInstruction, 27, 23);
        
    m_instruction.opcode = static_cast<Opcode>(op + static_cast<u32>(OpcodeMap::OP_MAP_SOPK));
    
    m_instruction.dst[0].field = getOperandField(sdst);
    m_instruction.dst[0].code = sdst;
    m_instruction.dst_count = 1;
        
    m_instruction.control.sopk = *reinterpret_cast<InstControlSOPK*>(&hexInstruction);
}

_{🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.}

## 📋 Pull Request Information **Original PR:** https://github.com/shadps4-emu/shadPS4/pull/613 **Author:** [@0xsegf4ult](https://github.com/0xsegf4ult) **Created:** 8/27/2024 **Status:** ✅ Merged **Merged:** 8/28/2024 **Merged by:** [@raphaelthegreat](https://github.com/raphaelthegreat) **Base:** `main` ← **Head:** `gcn_opcodes` --- ### 📝 Commits (7) - [`ad52474`](https://github.com/shadps4-emu/shadPS4/commit/ad524741d33026a7aeb22a1d93f85ebaf069c390) rebase on main branch impl of V_LSHL_B64 - [`de7f6e1`](https://github.com/shadps4-emu/shadPS4/commit/de7f6e11e612fd97c415ddad9b66b7e029e832e6) remove V_LSHR_B64 - [`64bacb2`](https://github.com/shadps4-emu/shadPS4/commit/64bacb20ce655a3db89c37c950c3dc65d24cdfec) fix S_CMPK_EQ_u32 - [`b0d300b`](https://github.com/shadps4-emu/shadPS4/commit/b0d300b153acdb028b2403f457caffcfabb35f12) fix conflicts - [`0fda82c`](https://github.com/shadps4-emu/shadPS4/commit/0fda82c8e30c29dbf71156463a847afee45da11c) fix broken merge - [`19c3569`](https://github.com/shadps4-emu/shadPS4/commit/19c3569645107bdde73e571e1ed68c58d10703b5) remove duplicate cases - [`01931cc`](https://github.com/shadps4-emu/shadPS4/commit/01931cc9061da0522cbc44c2893f047afdf934f5) remove duplicate declaration ### 📊 Changes **7 files changed** (+29 additions, -4 deletions) <details> <summary>View changed files</summary> 📝 `src/shader_recompiler/backend/spirv/emit_spirv_instructions.h` (+1 -0) 📝 `src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp` (+7 -0) 📝 `src/shader_recompiler/frontend/translate/scalar_alu.cpp` (+1 -1) 📝 `src/shader_recompiler/ir/ir_emitter.cpp` (+12 -2) 📝 `src/shader_recompiler/ir/ir_emitter.h` (+1 -1) 📝 `src/shader_recompiler/ir/opcodes.inc` (+1 -0) 📝 `src/shader_recompiler/ir/passes/constant_propagation_pass.cpp` (+6 -0) </details> ### 📄 Description - Implemented BitwiseAnd64 IR opcode and added it with BitwiseOr64 to the constant propagation pass - Fixed S_CMPK_EQ_U32 to use the correct operand Currently S_CMPK_EQ_U32 uses src[0] which is not defined for a SOPK instruction and this code always fails an assertion as the operand field is left undefined. ```c++ const IR::U32 src0{GetSrc(inst.src[0])}; ``` I moved this to inst.dst[0] as specified in the ISA documentation and in line with how the decoder parses SOPK instructions > S_CMPK_EQ_U32: SCC = (D.u == SIMM16). ```cpp void GcnDecodeContext::decodeInstructionSOPK(u32 hexInstruction) { u32 sdst = bit::extract(hexInstruction, 22, 16); u32 op = bit::extract(hexInstruction, 27, 23); m_instruction.opcode = static_cast<Opcode>(op + static_cast<u32>(OpcodeMap::OP_MAP_SOPK)); m_instruction.dst[0].field = getOperandField(sdst); m_instruction.dst[0].code = sdst; m_instruction.dst_count = 1; m_instruction.control.sopk = *reinterpret_cast<InstControlSOPK*>(&hexInstruction); } ``` --- <sub>🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.</sub>