[PR #310] [MERGED] 64 bits OP, impl V_ADDC_U32 & V_MAD_U64_U32 #1471

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opened 2026-02-27 21:12:42 +03:00 by kerem · 0 comments

kerem commented

2026-02-27 21:12:42 +03:00

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📋 Pull Request Information

Original PR: https://github.com/shadps4-emu/shadPS4/pull/310
Author: @viniciuslrangel
Created: 7/21/2024
Status: ✅ Merged
Merged: 7/27/2024
Merged by: @raphaelthegreat

Base: main ← Head: op_impl_2

📝 Commits (10+)

e23749b impl V_ADDC_U32 & V_MAD_U64_U32
510072b shader recompiler: add 64 bits version to get register / GetSrc
c73aff3 fix V_ADDC_U32 carry
21ce67e shader recompiler: removed automatic conversion to force_flt in GetSRc
09946f1 shader recompiler: auto cast between u32 and u64 during ssa pass
96b2cf1 shader recompiler: fix SetVectorReg64 & standardize switches-case
11d9fbd shader translate: fix overflow detection in V_ADD_I32
4d224d6 shader recompiler: more 64-bit work
df25708 shader recompiler: add V_MAD_U64_U32 vcc output
7e0e99e shader recompiler: removed unnecessary changes & missing consts

📊 Changes

12 files changed (+361 additions, -40 deletions)

View changed files

📝 src/shader_recompiler/backend/spirv/emit_spirv_instructions.h (+6 -2)
📝 src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp (+21 -2)
📝 src/shader_recompiler/frontend/opcodes.h (+4 -4)
📝 src/shader_recompiler/frontend/translate/translate.cpp (+198 -10)
📝 src/shader_recompiler/frontend/translate/translate.h (+7 -1)
📝 src/shader_recompiler/frontend/translate/vector_alu.cpp (+43 -1)
📝 src/shader_recompiler/ir/ir_emitter.cpp (+57 -10)
📝 src/shader_recompiler/ir/ir_emitter.h (+3 -3)
📝 src/shader_recompiler/ir/opcodes.inc (+6 -2)
📝 src/shader_recompiler/ir/passes/constant_propogation_pass.cpp (+10 -2)
📝 src/shader_recompiler/ir/passes/ssa_rewrite_pass.cpp (+5 -3)
📝 src/shader_recompiler/ir/value.h (+1 -0)

📄 Description

~~Still need to implement SSA rewrite auto cast between 64 and 32 bits~~

Fixed op src being wrongly forced to float

_{🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.}

## 📋 Pull Request Information **Original PR:** https://github.com/shadps4-emu/shadPS4/pull/310 **Author:** [@viniciuslrangel](https://github.com/viniciuslrangel) **Created:** 7/21/2024 **Status:** ✅ Merged **Merged:** 7/27/2024 **Merged by:** [@raphaelthegreat](https://github.com/raphaelthegreat) **Base:** `main` ← **Head:** `op_impl_2` --- ### 📝 Commits (10+) - [`e23749b`](https://github.com/shadps4-emu/shadPS4/commit/e23749bf0e23e5a9431565c8e08b90fa76ee8cda) impl V_ADDC_U32 & V_MAD_U64_U32 - [`510072b`](https://github.com/shadps4-emu/shadPS4/commit/510072b4f48801df4b0b29dfad19eafae03eba4f) shader recompiler: add 64 bits version to get register / GetSrc - [`c73aff3`](https://github.com/shadps4-emu/shadPS4/commit/c73aff3f8d74f1d3a064120de80ea41d66402509) fix V_ADDC_U32 carry - [`21ce67e`](https://github.com/shadps4-emu/shadPS4/commit/21ce67e8a0f84f21fb8bfce70f4864bd0618610d) shader recompiler: removed automatic conversion to force_flt in GetSRc - [`09946f1`](https://github.com/shadps4-emu/shadPS4/commit/09946f15a270074a436655869150389dff9876fb) shader recompiler: auto cast between u32 and u64 during ssa pass - [`96b2cf1`](https://github.com/shadps4-emu/shadPS4/commit/96b2cf1e61e499eeb65fb0e67f5ed844b3ec1f2a) shader recompiler: fix SetVectorReg64 & standardize switches-case - [`11d9fbd`](https://github.com/shadps4-emu/shadPS4/commit/11d9fbd20e1e3540aa9e8f3ade32e99107ebe4ba) shader translate: fix overflow detection in V_ADD_I32 - [`4d224d6`](https://github.com/shadps4-emu/shadPS4/commit/4d224d6bce2a754541a19afc34572568ff348170) shader recompiler: more 64-bit work - [`df25708`](https://github.com/shadps4-emu/shadPS4/commit/df257087d1c1f6189d47844ad6b9f2d42b298a3f) shader recompiler: add V_MAD_U64_U32 vcc output - [`7e0e99e`](https://github.com/shadps4-emu/shadPS4/commit/7e0e99e21d8a0580a1cdf9bf25738012225d38d7) shader recompiler: removed unnecessary changes & missing consts ### 📊 Changes **12 files changed** (+361 additions, -40 deletions) <details> <summary>View changed files</summary> 📝 `src/shader_recompiler/backend/spirv/emit_spirv_instructions.h` (+6 -2) 📝 `src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp` (+21 -2) 📝 `src/shader_recompiler/frontend/opcodes.h` (+4 -4) 📝 `src/shader_recompiler/frontend/translate/translate.cpp` (+198 -10) 📝 `src/shader_recompiler/frontend/translate/translate.h` (+7 -1) 📝 `src/shader_recompiler/frontend/translate/vector_alu.cpp` (+43 -1) 📝 `src/shader_recompiler/ir/ir_emitter.cpp` (+57 -10) 📝 `src/shader_recompiler/ir/ir_emitter.h` (+3 -3) 📝 `src/shader_recompiler/ir/opcodes.inc` (+6 -2) 📝 `src/shader_recompiler/ir/passes/constant_propogation_pass.cpp` (+10 -2) 📝 `src/shader_recompiler/ir/passes/ssa_rewrite_pass.cpp` (+5 -3) 📝 `src/shader_recompiler/ir/value.h` (+1 -0) </details> ### 📄 Description ~Still need to implement SSA rewrite auto cast between 64 and 32 bits~ Fixed op src being wrongly forced to float --- <sub>🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.</sub>